This invention relates generally to determining the timing of a data signal and, more particularly, to buffered architectures for determining the timing.
Phase-locked loops (PLLs) operate in a system, such as a disk drive, to synchronize the system and to improve signal-to-noise (SNR) ratios in the system. In a buffered architecture disk drive, an analog signal is read from a storage medium, such as a computer hard disk, and is digitized using an analog-to-digital (A/D) converter. The resulting asynchronous digital data is stored in a buffer, from which the asynchronous digital data is sampled. A clock signal controls the sampling to produce synchronous digital data. If the clock signal is out of phase with the synchronous digital data, errors may result in the output digital data.
In general, in one aspect, the invention is directed to determining a phase error in a data signal having first phase bits, second phase bits, and data between the first and second phase bits. This aspect of the invention features obtaining a first phase based on the first phase bits, obtaining a second phase based on the second phase bits, and determining a phase error of the data based on the first and second phases. One advantage of this aspect of the invention is that the phase error of the data can be determined from information in the data signal itself.
This aspect of the invention may include one or more of the following features. The first phase bits define a first function and the first phase is obtained by determining the phase of the first function. The second phase bits define a second function and the second phase is obtained by determining the phase of the second function. The phase error is determined by performing an interpolation, such as linear interpolation, using the first and second phases. The first and second phase bits may be parts of first and second data preambles, respectively.
This aspect may also include storing the data signal in a buffer, adjusting a clock signal based on the phase error, sampling the data from the buffer using the clock signal, detecting bits in the sampled data, obtaining a phase difference between a first waveform that corresponds to the detected bits and a second waveform that corresponds to the sampled data, and adjusting the clock signal based on the phase difference. The data may be re-sampled from the buffer using the clock signal, and then stored in another buffer, from which it is sampled.
In general, in another aspect, the invention is directed to determining a phase error in a data signal. This aspect of the invention features detecting bits in an original data signal, determining a phase error in the original data signal based on the detected bits, adjusting a clock signal based on the phase error, sampling the original data signal with the clock signal to produce a sampled data signal, and repeating detecting, determining, adjusting and sampling using the sampled data signal instead of the original data signal. By repeating the process, it is possible to iteratively determine timing, increasing its accuracy at each iteration.
This aspect of the invention may also include one or more of the following features. The phase error is determined by comparing a waveform that corresponds the detected bits to a waveform that corresponds to the original data signal. The original data signal includes synchronously data sampled from a buffer. A Viterbi detector, or other type of detector, may be used to perform the detecting.
In general, in another aspect, the invention is directed to determining a phase error in a data signal stored in a buffer. This aspect of the invention features detecting bits in an original data signal and determining a phase error in the original data signal based on the detected bits using a smoothing technique. The smoothing technique takes data before and after the bits into account, thereby increasing the accuracy of determination of the phase error.
This aspect of the invention may include one or more of the following features. The smoothing technique may be Kalman smoothing and may include determining a first phase difference between waveforms corresponding to the original data signal and the detected bits at first corresponding locations in the original data signal and the detected bits, determining a second phase difference between waveforms corresponding to the original data signal and the detected bits at second corresponding locations in the original data signal and the detected bits, and determining the phase error by obtaining a weighted value that is based on the first and second phase differences and the first and second corresponding locations.
The phase error, xcex8k, for a xe2x80x9ckthxe2x80x9d data bit, may be determined as follows:
xcex8k=xcex1k1xcex8k1+xcex1k2xcex8k2,
where xcex8k1 is the first phase difference, xcex1k1 is a weight assigned to the first corresponding locations, xcex8k2 is the second phase difference, and xcex1k2 is a weight assigned to the second corresponding locations. Values for xcex1k1 and xcex1k2 are assigned based on the first and second corresponding locations, respectively.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features and advantages of the invention will be apparent from the following description, drawings and claims.